H.264/AVC high definition intra coding implementation on multiprocessor system on chip technology architecture

Abstract : Exploiting the multiprocessor system on chip technology (MPSoC) is a promising way to improve the frame rate of latest video encoders. In this article, an MPSoC architecture for the intra prediction encoding chain of H.264/AVC high definition is proposed using SoCLib, an open platform for virtual prototyping of MPSoC architectures. Experimental results show a speedup of about 85% in processing time, compared with an execution based on a single central processing unit, with an acceptable final circuit area. The proposed parallelism does not affect the quality of the reconstructed video and bit rate. It takes into account the data loading latency constraint and the size of used memory requirement. The proposed architecture is validated on FPGA technology, using a technique that allows switching from a virtual platform to a hardware one.
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https://hal.archives-ouvertes.fr/hal-01369161
Contributor : Habib Mehrez <>
Submitted on : Tuesday, September 20, 2016 - 3:32:53 PM
Last modification on : Thursday, March 21, 2019 - 1:11:28 PM

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Nidhameddine Belhadj, Nejmeddine Bahri, Zied Marrakchi, Mohamed Ali Ben Ayed, Nouri Masmoudi, et al.. H.264/AVC high definition intra coding implementation on multiprocessor system on chip technology architecture. IET Computers & Digital Techniques, Institution of Engineering and Technology, 2015, 9 (5), pp.259--267. ⟨10.1049/iet-cdt.2014.0151⟩. ⟨hal-01369161⟩

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