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Communication Dans Un Congrès Année : 2004

Modular on chip multi processor for routing applications

Résumé

Simulation platforms for network processing still have difficulties in finding a good compromise betweenspeed and accuracy.This makes it difficult to identify the causes of performance bottlenecks: Are they caused by application, hardware architecture, or by a specificity of the operating system? We propose a simulation methodology for a multiprocessor network processing platform which contains sufficient detail to permit very precise simulation and performance evaluation whilestaying within reasonable limits of both specification and simulation time. As a case study, we show how a model can be developed for a IPv4 packet routing application, exhibiting the performance and scalability bottlenecks and can thus be used to reason about architectural alternatives.
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Dates et versions

hal-01365379 , version 1 (21-10-2019)

Identifiants

Citer

Saifeddine Berrayana, Etienne Faure, Daniela Genius, Frédéric Pétrot. Modular on chip multi processor for routing applications. Euro-Par 2004 - 10th European Conference on Parallel computing, Aug 2004, Pise, Italy. pp.847-855, ⟨10.1007/978-3-540-27866-5_113⟩. ⟨hal-01365379⟩
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