Beyond Gbps Turbo Decoder on Multi-Core CPUs

Adrien Cassagne (1, 2, 3) , Thibaud Tonnellier (2) , Camille Leroux (4) , Bertrand Le Gal (2) , Olivier Aumage (1) , Denis Barthou (1)

1 STORM - STatic Optimizations, Runtime Methods
2 IMS - Laboratoire de l'intégration, du matériau au système
3 UB - Université de Bordeaux
4 IM2NP - Institut des Matériaux, de Microélectronique et des Nanosciences de Provence

This paper presents a high-throughput implementation of a portable software turbo decoder. The code is optimized for traditional multi-core CPUs (like x86) and it is based on the Enhanced max-log-MAP turbo decoding variant. The code follows the LTE-Advanced specification. The key of the high performance comes from an inter-frame SIMD strategy combined with a fixed-point representation. Our results show that proposed multi-core CPU implementation of turbo-decoders is a challenging alternative to GPU implementation in terms of throughput and energy efficiency. On a high-end processor, our software turbo-decoder exceeds 1 Gbps information throughput for all rate-1/3 LTE codes with K < 4096.

Domaines: Algorithme et structure de données [cs.DS]; Calcul parallèle, distribué et partagé [cs.DC]; Bibliothèque électronique [cs.DL]

Adrien Cassagne, Thibaud Tonnellier, Camille Leroux, Bertrand Le Gal, Olivier Aumage, et al.. Beyond Gbps Turbo Decoder on Multi-Core CPUs. The 10th International Symposium on Turbo Codes and Iterative Information Processing (ISTC 2016), Sep 2016, Brest, France. ⟨10.1109/ISTC.2016.7593092⟩. ⟨hal-01363980⟩