RWT: Suppressing Write-Through Cost When Coherence is Not Needed

Abstract : —In shared-memory multicore architectures, handling a write cache operation is more complicated than in single-processor systems. A cache line may be present in more than one private L1 cache. Any cache willing to write this line must inform all the other sharers. Therefore, it is necessary to implement a cache coherence protocol for multicore architectures. At present, directory based protocols are popular cache coherence protocols in both industry and academic domains because of their reduced coherence traffic compared to snooping protocols, at the expense of an indirection. The write policy – write through or write back – is crucial in the protocol design. The write-through policy reduces the bandwidth because it augments the write traffic in the interconnection network, and also augments the energy consumption. However, it can efficiently solve the false sharing problem via write updates. In this paper, we introduce a new way to reduce the write traffic of a write-through coherence protocol by combining write-through coherence with a write-back policy for non coherent lines. The baseline write-through used as reference is a scalable hybrid invalidate/update protocol. Simulation results show that with our enhanced protocol, we can reduce at least by 50% the write traffic in the interconnection network, and gain up to 20% performance compared with the baseline write-through protocol.
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Hao Liu, Clément Dévigne, Lucas Garcia, Quentin L. Meunier, Franck Wajsbürt, et al.. RWT: Suppressing Write-Through Cost When Coherence is Not Needed. 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Jul 2015, Montpellier, France. pp.434-439, ⟨10.1109/ISVLSI.2015.35⟩. ⟨hal-01362872⟩

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