A new SIMD iterative connected component labeling algorithm

Lionel Lacassagne (1) , Laurent Cabaret (2) , Daniel Etiemble (2) , Farouk Hebbache (2) , Andrea Petreto (2)

1 ALSOC - Architecture et Logiciels pour Systèmes Embarqués sur Puce
2 LRI - Laboratoire de Recherche en Informatique

This paper presents a new multi-pass iterative algorithm for Connected Component Labeling. The performance of this algorithm is compared to those of State-of-the-Art two-pass direct algorithms. We show that thanks to the parallelism of the SIMD multi-core processors and an activity matrix that avoids useless memory access, such a kind of algorithm has performance that comes closer and closer to direct ones. This new tiled iterative algorithm has been benchmarked on four generations of Intel Xeon processors: 2×4-core Nehalem, 2×12-core Ivy-Bridge, 2×14-core Haswell and 57-core Knight Corner. Macro meta-programming was used to design a unique code for SSE, AVX2 and KNC SIMD instruction set.

Mots clés: direct vs iterative algorithms; Intel Xeon-Phi; KNC; AVX; SSE; SIMDization; Connected Component Labeling algorithm

Domaines: Algorithme et structure de données [cs.DS]; Architectures Matérielles [cs.AR]; Traitement des images [eess.IV]; Traitement du signal et de l'image [eess.SP]; Vision par ordinateur et reconnaissance de formes [cs.CV]; Traitement du signal et de l'image [eess.SP]; Arithmétique des ordinateurs; Calcul parallèle, distribué et partagé [cs.DC]; Génie logiciel [cs.SE]; Mathématique discrète [cs.DM]; Robotique [cs.RO]

Lionel Lacassagne, Laurent Cabaret, Daniel Etiemble, Farouk Hebbache, Andrea Petreto. A new SIMD iterative connected component labeling algorithm. Principles and Practice of Parallel Programming / WVMVP, ACM, Mar 2016, Barcelone, Spain. ⟨10.1145/2870650.2870652⟩. ⟨hal-01361101⟩