A new SIMD iterative connected component labeling algorithm

Abstract : This paper presents a new multi-pass iterative algorithm for Connected Component Labeling. The performance of this algorithm is compared to those of State-of-the-Art two-pass direct algorithms. We show that thanks to the parallelism of the SIMD multi-core processors and an activity matrix that avoids useless memory access, such a kind of algorithm has performance that comes closer and closer to direct ones. This new tiled iterative algorithm has been benchmarked on four generations of Intel Xeon processors: 2×4-core Nehalem, 2×12-core Ivy-Bridge, 2×14-core Haswell and 57-core Knight Corner. Macro meta-programming was used to design a unique code for SSE, AVX2 and KNC SIMD instruction set.
Complete list of metadatas

Cited literature [28 references]  Display  Hide  Download

https://hal.archives-ouvertes.fr/hal-01361101
Contributor : Lionel Lacassagne <>
Submitted on : Saturday, September 24, 2016 - 3:38:30 PM
Last modification on : Thursday, March 21, 2019 - 1:03:51 PM
Long-term archiving on : Sunday, December 25, 2016 - 12:15:23 PM

File

PPoPP_WPMVP_2016_SIMD_labeling...
Publisher files allowed on an open archive

Identifiers

Citation

Lionel Lacassagne, Laurent Cabaret, Daniel Etiemble, Farouk Hebbache, Andrea Petreto. A new SIMD iterative connected component labeling algorithm. Principles and Practice of Parallel Programming / WVMVP, ACM, Mar 2016, Barcelone, Spain. ⟨10.1145/2870650.2870652⟩. ⟨hal-01361101⟩

Share

Metrics

Record views

957

Files downloads

618