Design Productivity of a High Level Synthesis Compiler versus HDL

Maxime Pelcat; Cédric Bourrasset; Luca Maggiani; François Berry

doi:10.1109/SAMOS.2016.7818341

Design Productivity of a High Level Synthesis Compiler versus HDL

Maxime Pelcat ^{1, 2} Cédric Bourrasset ^{1, 3} Luca Maggiani ^{1, 4} François Berry ¹

1 IP - Institut Pascal

2 IETR - Institut d'Electronique et de Télécommunications de Rennes

3 Atos/Bull Center for Excellence in Parallel Programming

4 Scuola Superiore Sant'Anna [Pisa]

Abstract : The complexity of hardware systems is currently growing faster than the productivity of system designers and programmers. This phenomenon is called Design Productivity Gap and results in inflating design costs. In this paper, the notion of Design Productivity is precisely defined, as well as a metric to assess the Design Productivity of a High-Level Synthesis (HLS) method versus a manual hardware description. The proposed Design Productivity metric evaluates the trade-off between design efficiency and implementation quality. The method is generic enough to be used for comparing several HLS methods of different natures, opening opportunities for further progress in Design Productivity. To demonstrate the Design Productivity evaluation method, an HLS compiler based on the CAPH language is compared to manual VHDL writing. The causes that make VHDL lower level than CAPH are discussed. Versions of the sub-pixel interpolation filter from the MPEG HEVC standard are implemented and a design productivity gain of 2.3× in average is measured for the CAPH HLS method. It results from an average gain in design time of 4.4× and an average loss in quality of 1.9×.

Keywords : High Level Synthesis Design Productivity FPGA

Type de document :

Communication dans un congrès

2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2016), Jul 2016, Agios Konstantinos, SAMOS, Greece. Proceedings of the 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2016), Samos, Greece, 2016, 〈10.1109/SAMOS.2016.7818341〉

Domaine :

Sciences de l'ingénieur [physics] / Traitement du signal et de l'image

Informatique [cs] / Architectures Matérielles [cs.AR]

Informatique [cs] / Systèmes embarqués

Informatique [cs] / Ingénierie assistée par ordinateur

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https://hal.archives-ouvertes.fr/hal-01358210
Contributeur : Maxime Pelcat <>
Soumis le : mercredi 31 août 2016 - 12:07:58
Dernière modification le : jeudi 7 février 2019 - 17:50:22
Document(s) archivé(s) le : vendredi 2 décembre 2016 - 01:00:03

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Maxime Pelcat, Cédric Bourrasset, Luca Maggiani, François Berry. Design Productivity of a High Level Synthesis Compiler versus HDL. 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2016), Jul 2016, Agios Konstantinos, SAMOS, Greece. Proceedings of the 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2016), Samos, Greece, 2016, 〈10.1109/SAMOS.2016.7818341〉. 〈hal-01358210〉

Design Productivity of a High Level Synthesis Compiler versus HDL

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