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Early system failure prediction by using aging in situ monitors: Methodology of implementation and application results

Abstract : With CMOS technology scaling, it becomes more and more difficult to guarantee circuit functionality for all process, voltage, temperature (PVT) corners. Moreover, circuit wear-out degradation lead to additional temporal variations, resulting in an important increase of design margins when targeting specific reliable systems (automotive or health care embedded applications) [1]. Adding pessimistic timing margin to guarantee all operating points under worse case conditions is no more acceptable due to the huge impact on design costs, such as up to 10% increase of slack time, with an upward trend as technology moves further.
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https://hal.archives-ouvertes.fr/hal-01357213
Contributor : Lucie Torella <>
Submitted on : Monday, August 29, 2016 - 2:30:24 PM
Last modification on : Tuesday, May 11, 2021 - 11:37:50 AM

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Distributed under a Creative Commons Attribution - NonCommercial 4.0 International License

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  • HAL Id : hal-01357213, version 1

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Lorena Anghel, A. Benhassain, A. Sivadasan. Early system failure prediction by using aging in situ monitors: Methodology of implementation and application results. IEEE 34th VLSI Test Symposium (VTS'16), Apr 2016, Las Vegas, NE, United States. ⟨hal-01357213⟩

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