FPGA design of EKF block accelerator for 3D visual SLAM

Daniel Tortei (1, 2) , Jonathan Piat (2) , Michel Devy (2)

1 Department of Computing and Automation
2 LAAS-RAP - Équipe Robotique, Action et Perception

This paper deals with the evaluation of a dedicated architecture to be integrated into an embedded system typically mounted on a micro-aerial vehicle or on smart devices held by an operator. This system performs an Extended Kalman Filter (EKF) based visual odometry (VO) algorithm. An efficient hardware architecture conceived as a systolic array co-processor for EKF loop acceleration is presented. Due to severe limitations in terms of power consumption, real-time performance and physical characteristics of the system (i.e. compactness and weight), this algorithm is implemented entirely as a System On a programmable Chip (SoC) on the Zynq-7020 device. This heterogeneous (processor with reconfigurable hardware) platform consumes less power than a standard microprocessor and provides powerful parallel data processing capabilities: applying hardware/software (hw/sw) co-design allows real-time throughput with a very low power-per-feature rate.

Mots clés: AHP; Co-processor; Visual EKF SLAM; SoC System on Chip; FPGA - field-programmable gate array

Domaines: Robotique [cs.RO]; Traitement du signal et de l'image [eess.SP]; Electronique

Daniel Tortei, Jonathan Piat, Michel Devy. FPGA design of EKF block accelerator for 3D visual SLAM. Computers and Electrical Engineering, 2016, ⟨10.1016/j.compeleceng.2016.05.003⟩. ⟨hal-01354883⟩