Investigation of the power-clock network impact on adiabatic logic

Nicolas Jeanniot (1) , Aida Todri-Sanial (1) , Pascal Nouet (1) , Gaël Pillonnet (2) , Hervé Fanet (2)

1 SysMIC - Conception et Test de Systèmes MICroélectroniques
2 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information

Adiabatic logic is architecture design style which seems to be a good candidate to reduce the power consumption of digital cores. One key difference is that the power supply is also the clock signal. A lot of work on different adiabatic logic families has been done but the impact of the power supply and the power-clock network still remains to be studied. In this paper, we investigate the power-clock network effect on adiabatic energy dissipation. We derive closed-form analytical formulas to represent the output signal voltage and energy dissipation while taking into account the parasitic impedance of the power-clock network with respect to switching frequency such that adiabatic conditions are still met. Experiments, based on simulation, show that the power-clock network impacts both the energy efficiency of the circuit and its frequency.

Mots clés: Adiabatic Logic; Power-Clock Distribution Network; Power Efficiency

Domaines: Electronique

Nicolas Jeanniot, Aida Todri-Sanial, Pascal Nouet, Gaël Pillonnet, Hervé Fanet. Investigation of the power-clock network impact on adiabatic logic. SPI: Signal and Power Integrity, May 2016, Turin, Italy. ⟨10.1109/SaPIW.2016.7496270⟩. ⟨hal-01348476⟩