Zephyr: a Static Timing Analyzer integrated in a trans-hierarchical refinement design flow

Christophe Alexandre 1 Marek Sroka 1 Hugo Clément 1 Christian Masson
1 CIAN - Circuits Intégrés Numériques et Analogiques
LIP6 - Laboratoire d'Informatique de Paris 6
Abstract : The evolution of silicon technologies has fundamentally changed the physical design EDA flow, which now has to go through a progressive refinement process where interconnections evolve seamlessly from logic to final detailed routing. Furthermore the level of integration reached makes mandatory the use of hierarchical enabled design methodologies. In this paper, we present Zephyr: an Elmore Delay Static Timing Analysis engine tightly integrated in the open academic Coriolis EDA physical design platform on which tools act as algorithmic engines operating on an integrated C++ database around which they consistently interact and collaborate. Coriolis provides high level C++ and Python APIs and a unified and consistent hierarchical VLSI data model through all the design steps from logic down to final layout. We discuss here more specifically the integration issues and concepts used to support timing analysis through the progressive refinement of hierarchical designs.
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https://hal.archives-ouvertes.fr/hal-01338439
Contributeur : Lip6 Publications <>
Soumis le : mardi 28 juin 2016 - 15:56:55
Dernière modification le : jeudi 21 mars 2019 - 14:16:22

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Christophe Alexandre, Marek Sroka, Hugo Clément, Christian Masson. Zephyr: a Static Timing Analyzer integrated in a trans-hierarchical refinement design flow. PATMOS Power and Timing Modeling Optimization and Simulation, Sep 2006, Montpellier, France. pp.319-328, ⟨10.1007/11847083_31⟩. ⟨hal-01338439⟩

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