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STESOC: A Software-Based Test-Access-Mechanism Controller

Abstract : Software-based test of SoCs consists in testing IP cores using embedded processor cores. Previously proposed solutions are usually ad-hoc. Therefore, this paper presents STESOC, a software-based Test Access Mechanism for SoCs containing standard-wrapped IP cores. Under the control of the embedded microprocessor, a dedicated test-coprocessor tests the remaining components. Using the ITC02 SoC benchmarks a comparison is done between the STESOC architecture and a classical bus-based strategy.
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Submitted on : Thursday, June 23, 2016 - 2:46:34 PM
Last modification on : Friday, October 2, 2020 - 1:58:02 PM


  • HAL Id : hal-01336645, version 1


Matthieu Tuna, Mounir Benabdenbi, Alain Greiner. STESOC: A Software-Based Test-Access-Mechanism Controller. ETS IEEE European Test Symposium, May 2006, Southampton, United Kingdom. pp.91-96. ⟨hal-01336645⟩



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