High-Level Virtual Prototyping of Signal Integrity in Bus Communication

Ruomin Wang (1) , Julien Denoulet (1) , Sylvain Feruglio (1) , Farouk Vallette (1) , Patrick Garda (1)

1 SYEL - Systèmes Electroniques

In this paper, a novel methodology for high-level modeling of bus communication in embedded systems is introduced. It allows dynamic evaluation of their signal integrity characteristics at the virtual prototyping step (i.e. before physical realization). The method is based on the association of functional and non-functional modules. Functional modules represent the ideal behavior of the system, while non-functional modules use neural networks to model signal integrity effects. This approach was implemented in SystemC-AMS, using the timed data flow model of computation. The method is illustrated by an USB 3.0 application, where modular and parameterizable models are introduced. The method achieved good accuracy (<5 %) while allowing significant simulation speedup (up to ×2000), compared to SPICE-based reference models. This methodology can be used to perform early signal integrity analysis in the virtual prototyping of bus communication in embedded systems.

Mots clés: bus communication; embedded systems; high level; non-functional; modeling; neural network; signal integrity; simulation; SystemC-AMS; system level; timed data flow; virtual prototyping

Domaines: Electronique

Ruomin Wang, Julien Denoulet, Sylvain Feruglio, Farouk Vallette, Patrick Garda. High-Level Virtual Prototyping of Signal Integrity in Bus Communication. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2016, 6 (6), pp.864-872. ⟨10.1109/TCPMT.2016.2558288⟩. ⟨hal-01330855⟩