An ESL framework for low power architecture design space exploration
Résumé
Designers of complex SoCs have to face the issue of tuning their design to achieve low power consumption without compromising performance. A set of complementary techniques at hardware level are able to reduce power consumption but most of these techniques impact system performance and behavior. At register transfer level, low power design flows are available. Unfortunately, equivalent design flows at transactional level are missing. In this paper we describe how a power/clock intent could be described at transactional level using a separation of concerns process and how the transactional simulation code merging functional and power behaviors can be generated automatically using a model-driven engineering approach.
Mots clés
transactional level
transactional simulation code
Clocks
Computer architecture
Control systems
Hardware
Model driven engineering
Power demand
Unified modeling language
low power
model-driven engineering
separation of concerns
simulation
low power consumption
integrated circuit design
system-on-chip
low-power electronics
ESL framework
functional behavior
complex SoC
low power architecture design space exploration
hardware level
power behavior
power/clock intent
register transfer level
system performance