Low latency combination of parallelized single-pass LVCSR systems

Abstract : Recent progress in hardware technology, especially multi-core CPUs, offer new perspectives to accelerate software by parallelizing the computing process. But, it is still considered as a difficult task to parallelize the execution of an ASR system, as the different steps are usually sequential. This paper addresses some opportunities offered by parallelism for ASR system combination: the proposed approach consists in making on the fly combination , whereas the classical approach consists in only combining final outputs. This approach is particularly relevant for applications which need a very low latency response. This paper presents some preliminary results which show a 14% relative reduction in Word Error Rate with a limited impact on the latency due to ASR system combination. Index Terms: LVCSR system harnessing, driven decoding , local ROVER combination.
Type de document :
Communication dans un congrès
Interspeech, Sep 2012, Portland, United States
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Contributeur : Bibliothèque Universitaire Déposants Hal-Avignon <>
Soumis le : lundi 9 mai 2016 - 16:46:05
Dernière modification le : mardi 5 mars 2019 - 01:39:17


  • HAL Id : hal-01313238, version 1



Fethi Bougares, Mickael Rouvier, Yannick Estève, Georges Linarès. Low latency combination of parallelized single-pass LVCSR systems. Interspeech, Sep 2012, Portland, United States. 〈hal-01313238〉



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