At-Speed Testing of Core-Based System-On-Chip Using an Embedded Micro-Tester

Abstract : In SoC designs, limited test access to internal cores, low-cost external tester's lack of accuracy and slow frequencies make application of at-speed tests impractical. Therefore, this paper presents an embedded micro-tester for testing IEEE1500-compliant SoCs. In the proposed approach, the test program is no more executed by the external tester but by the embedded micro-tester. Under the control of the embedded SoC microprocessor, the micro-tester executes the test programs stored outside of the SoC in an external memory. The micro-tester supports stuck-at testing as well as both at-speed testing techniques: launch-on-last-shift (LOLS) and launch-on-capture (LOC). Using the ITC'02 benchmarks, experimental results are presented: test application time, test data volume and area overhead.
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Conference papers
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https://hal.archives-ouvertes.fr/hal-01311492
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Submitted on : Wednesday, May 4, 2016 - 11:56:31 AM
Last modification on : Thursday, March 21, 2019 - 1:03:50 PM

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Matthieu Tuna, Mounir Benabdenbi, Alain Greiner. At-Speed Testing of Core-Based System-On-Chip Using an Embedded Micro-Tester. VTS IEEE VLSI Test Symposium, May 2007, Berkeley, California, United States. pp.447-454, ⟨10.1109/VTS.2007.16⟩. ⟨hal-01311492⟩

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