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Communication Dans Un Congrès Année : 2007

Systematic Comparison between the Asynchronous and the Multi-Synchronous Implementations of a Network on Chip Architecture

Résumé

This paper presents a systematic comparison between two different implementations of a distributed network on chip: fully asynchronous and multi-synchronous. The NoC architecture has been designed to be used in a globally asynchronous locally synchronous clusterized multi processors system on chip. The 5 relevant parameters are silicon area, network saturation threshold, communication throughput, packet latency and power consumption. Both architectures have been physically implemented and simulated by SystemC/VHDL co-simulation. The electrical parameters have also been evaluated by post layout SPICE simulation for a 90nm CMOS fabrication process, taking into account the long wire effects.
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hal-01311482 , version 1 (04-05-2016)

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Abbas Sheibanyrad, Ivan Miro Panades, Alain Greiner. Systematic Comparison between the Asynchronous and the Multi-Synchronous Implementations of a Network on Chip Architecture. DATE Design Automation and Test in Europe Conference 2007, Apr 2007, Nice, France. pp.1090-1095, ⟨10.1109/DATE.2007.364439⟩. ⟨hal-01311482⟩
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