Systematic Comparison between the Asynchronous and the Multi-Synchronous Implementations of a Network on Chip Architecture

Abstract : This paper presents a systematic comparison between two different implementations of a distributed network on chip: fully asynchronous and multi-synchronous. The NoC architecture has been designed to be used in a globally asynchronous locally synchronous clusterized multi processors system on chip. The 5 relevant parameters are silicon area, network saturation threshold, communication throughput, packet latency and power consumption. Both architectures have been physically implemented and simulated by SystemC/VHDL co-simulation. The electrical parameters have also been evaluated by post layout SPICE simulation for a 90nm CMOS fabrication process, taking into account the long wire effects.
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Conference papers
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https://hal.archives-ouvertes.fr/hal-01311482
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Submitted on : Wednesday, May 4, 2016 - 11:47:57 AM
Last modification on : Thursday, March 21, 2019 - 1:03:53 PM

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Abbas Sheibanyrad, Ivan Miro Panades, Alain Greiner. Systematic Comparison between the Asynchronous and the Multi-Synchronous Implementations of a Network on Chip Architecture. DATE Design Automation and Test in Europe Conference 2007, Apr 2007, Nice, France. pp.1090-1095, ⟨10.1109/DATE.2007.364439⟩. ⟨hal-01311482⟩

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