Hardware runtime verification of embedded software in SoPC

Dimitry Solet (1) , Jean-Luc Béchennec (2) , Mikaël Briday (2) , Sébastien Faucou (2) , Sébastien Pillement (1)

1 IETR - Institut d'Électronique et des Technologies du numéRique
2 IRCCyN - Institut de Recherche en Communications et en Cybernétique de Nantes

This paper discusses an implementation of runtime verification for embedded software running on a System-on- Programmable-Chip (SoPC) composed of a microcontroller and a FPGA. The goal is to verify at runtime that the execution of the software on the microcontroller conforms to a set of properties. To do so, a minimal instrumentation of the software is used to send events to a set of monitors implemented in the FPGA. These monitors are synthesized from a formal specification of the expected behavior of the system expressed as a set of past-time linear temporal logic (ptLTL) formula.

Mots clés: formal specification; past-time linear temporal logic formulas; software execution; FPGA; microcontroller; system-on-programmable-chip; embedded software; hardware runtime verification; SoPC; ptLTL formulas

Domaines: Autre

Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Sébastien Pillement. Hardware runtime verification of embedded software in SoPC. 2016 11th IEEE Symposium on Industrial Embedded Systems (SIES), May 2016, Cracovie, Poland. SIES 2016 paper 16, ⟨10.1109/sies.2016.7509425⟩. ⟨hal-01307973⟩