HW/SW Codesign of the H. 263 Video Coder

Ahmed Ben Atitallah (1) , Patrice Kadionik (2) , Fahmi Ghozzi (1) , Patrice Nouel (2) , Nouri Masmoudi (1) , Hervé Levi (2)

1 LETI - Laboratoire d'électronique et des technologies de l'Information [Sfax]
2 IMS - Laboratoire de l'intégration, du matériau au système

In this paper, we propose an optimized real-time H.263 video coder. The coder has been implemented in one FPGA device as HW/SW partitioned system. We made time analysis and optimization of the H.263 coder. On the basis of the achieved results, we decided for hardware implementation of the discrete cosine transform (DCT).Remaining parts were realized in software with NIOS II softcore processor. H.263 coder (NIOS II processor, DCT core) has described by the VHDL language and implemented in Stratix EP1S10 FPGA. Finally, the coder has been tested on the Altera Stratix development board.

Mots clés: H.263; FPGA; HW/SW codesign

Domaines: Micro et nanotechnologies/Microélectronique

Ahmed Ben Atitallah, Patrice Kadionik, Fahmi Ghozzi, Patrice Nouel, Nouri Masmoudi, et al.. HW/SW Codesign of the H. 263 Video Coder. ccece: Canadian Conference on Electrical and Computer Engineering , May 2006, ottawa, Canada. ⟨10.1109/CCECE.2006.277632⟩. ⟨hal-01306422⟩