An Efficient FPGA parallel Architecture for H.264/AVC Intra Prediction Algorithm
Résumé
In Motion Picture Experts Group (MPEG) and Video Coding Experts Group (VCEG) standards, intra prediction is used to eliminate the spatial redundancy. Given that the intra prediction stage is very complex in terms of computational effort, a hardware implementation on a re-configurable circuit is crucial for the requirements of different real-time multimedia applications. In this paper, we present novel hardware architecture for real-time implementation of intra prediction algorithm used in H.264 Advanced Video Coding (AVC) baseline profile video coding standard. This hardware is designed to be used as part of a complete H.264 video coding system for videoconference applications. We use an approach based on a novel organization of the intra prediction equations. This architecture presents minimum latency, maximum throughput, full utilization of hardware resources and combining both pipelining and parallel processing techniques. The proposed architecture is implemented in VHDL. On ALTERA Stratix II FPGA, the VHDL code is verified to work at 300 MHz for the luma intra prediction 4x4 architecture and 176 MHz for the luma intra prediction 16x16.