HW/SW TQ/IQT design for H.264/AVC
Résumé
In this paper, we present a HW/SW design for transform and quantization blocks to be used in the H.264/AVC prediction modes. The design is described in VHDL language and synthesized to Altera Stratix II FPGA and to TSMC 0.18μm standard-cells. In addition, a SoPC implementation and validation of the proposed design as an IP core is presented using the embedded FPGA development board.