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Interval arithmetic on the Cell processor

Abstract : The Cell processor is a new processor [2], designed by IBM, Sony and Toshiba, with an innovative architecture based on 8 Synergistic Processor Elements on the same chip. Each SPE contains a synergetic processing unit (SPU), a local memory (256KB of memory for the code and the data) and a memory flow controller. The SPU [1] is composed of a 4-way SIMD single precision FPU (SpSPU) and a 1-way SIMD double precision (DpSPU). Today, the peak rate is around 200 Gflops. Each SpSPU can perform 25.6 GFlops whereas DpSPU can only do 1.8GFlops. But SpSPU has only the rounding mode toward zero and no underflow and overflow whereas the DpSPU is fully IEEE 754 compliant. In order to deal efficiently with interval arithmetic [3] with only rounding mode toward zero, we discuss different ways to represent intervals and compare them on the SpSPU and on the DpSPU.
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Submitted on : Monday, April 18, 2016 - 3:02:08 PM
Last modification on : Thursday, March 21, 2019 - 2:17:33 PM


  • HAL Id : hal-01303667, version 1


Stef Graillat, Jean-Luc Lamotte, Siegfried M. Rump, Svetoslav Markov. Interval arithmetic on the Cell processor. 13th GAMM - IMACS International Symposium on Scientific Computing, Computer Arithmetic and Verified Numerical Computations SCAN'08, Sep 2008, El Paso, Texas, United States. pp.54-54. ⟨hal-01303667⟩



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