A New Coarse-grained FPGA Architecture Exploration Environment

Abstract : This paper presents an exploration environment for the design of 2D island-style coarse grained FPGA architectures. An architecture description file defines various architectural parameters including the definition of new coarse grained blocks, the positioning of blocks in the architecture and the selection of routing network. Once the initial architecture is defined, a software flow places and routes a target netlist on the generated architecture. The placement cost of a netlist is optimized either by changing the position of netlist instances on its respective blocks or by changing the position of blocks on the architecture. A single FPGA architecture can also be obtained for mapping a set of netlists at mutually exclusive times. It has been found that the sum of the placement costs of all the netlists is found to be minimum if all the netlists are used to get a single architecture. A set of DSP test-benches is used to show the effectiveness of the various techniques used in this work.
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Conference papers
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https://hal.archives-ouvertes.fr/hal-01301527
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Submitted on : Tuesday, April 12, 2016 - 2:05:57 PM
Last modification on : Thursday, March 21, 2019 - 1:09:06 PM

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Husain Parvez, Zied Marrakchi, Umer Farooq, Habib Mehrez. A New Coarse-grained FPGA Architecture Exploration Environment. ICFPT International Conference on Field-Programmable Technology, Dec 2008, Taipei, Taiwan. pp.285-288, ⟨10.1109/FPT.2008.4762399⟩. ⟨hal-01301527⟩

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