Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture

Ivan Miro Panades (1) , Fabien Clermidy , Pascal Vivet , Alain Greiner (1)

1 ALSOC - Architecture et Logiciels pour Systèmes Embarqués sur Puce

This paper presents a physical implementation of the DSPIN network-on-chip in the FAUST architecture. FAUST is a stream-oriented multi- application SoC platform for telecommunications addressing IEEE 802.11a and MC-CDMA standards. The original asynchronous network-on-chip (ANOC) of FAUST has been replaced by the multi-synchronous DSPIN network-on-chip. In this paper, we analyze how the DSPIN network-on-chip, originally designed to support shared memory and multi-processors architectures, can support stream-oriented architectures. The physical implementation of both ANOC and DSPIN are presented. Finally, a comparison between ANOC and DSPIN designs in a 130 nm technology is carried out in terms of area, throughput, packet latency, and power consumption.

Domaines: Informatique [cs]

Ivan Miro Panades, Fabien Clermidy, Pascal Vivet, Alain Greiner. Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture. NoC ACM/IEEE International Symposium on Networks-on-Chip, Apr 2008, Newcastle, United Kingdom. pp.139-148, ⟨10.1109/NOCS.2008.4492733⟩. ⟨hal-01299217⟩