Automatic Layout Generator of Domain Specific FPGA:

Abstract : This paper presents an automated method of generating an FPGA layout. The main purpose of developing a generator is to reduce the overall FPGA design time with limited area penalty. This generator works in two phases. In the first phase, it generates a partial layout using generic parameterized algorithms. The partial layout is generated to obtain a fast bitstream configuration mechanism, an efficient power routing and a balanced clock distribution network. In the second phase, the generator completes the remaining layout using automatic placer and router. This two-phase technique allows better maneuvering of the layout according to initial constraints. The proposed method is validated by generating the layout of an island-style FPGA which includes hardware support for the mitigation of single event upsets (SEU). The FPGA layout is generated in a symbolic standard cell library which allows easy migration to any layout technology. This layout is successfully migrated and taped out in 130 nm technology.
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Conference papers
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https://hal.archives-ouvertes.fr/hal-01299216
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Submitted on : Thursday, April 7, 2016 - 1:27:40 PM
Last modification on : Thursday, March 21, 2019 - 1:13:05 PM

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Hayder Mrabet, Husain Parvez, Zied Marrakchi, Habib Mehrez. Automatic Layout Generator of Domain Specific FPGA:. ICM International Conference on Microelectronics, Dec 2008, Sharjah, United Arab Emirates. pp.183-186, ⟨10.1109/ICM.2008.5393493⟩. ⟨hal-01299216⟩

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