Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing

Emna Amouri (1) , Hayder Mrabet , Zied Marrakchi (2) , Habib Mehrez (1)

1 CIAN - Circuits Intégrés Numériques et Analogiques
2 ALSOC - Architecture et Logiciels pour Systèmes Embarqués sur Puce

In this paper, we propose placement and routing techniques to deal with the timing unbalance problem in wave dynamic differential logic (WDDL) circuits. First, we study the impact of placement on the delay unbalance in a tree-based FPGA. Then, we propose an adaptation to the Pathfinder routing algorithm to improve the delay balance. The experimental results demonstrate that our placement and routing techniques reduce the delay unbalance significantly. They achieve 93% of average timing balancing improvement in WDDL designs.

Domaines: Informatique [cs]

Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez. Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing. ReConFig International Conference on Reconfigurable Computing and FPGAs 2009, Dec 2009, Cancun, Mexico. pp.201-206, ⟨10.1109/ReConFig.2009.44⟩. ⟨hal-01295098⟩