Hierarchical Sizing and Biasing of Analog Firm Intellectual Properties

Ramy Iskander (1) , Marie-Minerve Louërat (1) , Andreas Kaiser (2, 3)

1 CIAN - Circuits Intégrés Numériques et Analogiques
2 IEMN - Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520
3 MICROELEC SI - IEMN - Microélectronique Silicium - IEMN

We demonstrate hierarchical sizing and biasing methodology in CAIRO+ that automatically generates suitable designs plans used to compute the DC operating point and dimensions for analog firm IPs.

Domaines: Informatique [cs]

Ramy Iskander, Marie-Minerve Louërat, Andreas Kaiser. Hierarchical Sizing and Biasing of Analog Firm Intellectual Properties. DATE University Booth, Mar 2009, Nice, France. pp.1-2. ⟨hal-01295050⟩