C. Hanen and A. Munier, Cyclic scheduling on parallel processors: An overview Scheduling theory and its applications, J. Wiley and sons, 1994.

B. R. Rau, Dynamically scheduled VLIW processors, Proceedings of the 26th Annual International Symposium on Microarchitecture, pp.80-92, 1993.
DOI : 10.1109/MICRO.1993.282744

V. H. Allan, R. B. Jones, R. M. Lee, and S. J. Allan, Software pipelining, ACM Computing Surveys, vol.27, issue.3, pp.367-432, 1995.
DOI : 10.1145/212094.212131

B. R. Rau, Iterative modulo scheduling, Proceedings of the 27th annual international symposium on Microarchitecture , MICRO 27, pp.63-74, 1994.
DOI : 10.1145/192724.192731
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.304.8660

C. Artigues and B. D. Dinechin, Resource-Constrained Project Scheduling: Models, Algorithms , Extensions and Applications, C. Artigues, S. Demassey, E. Nron, 2008.
DOI : 10.1002/9780470611227
URL : https://hal.archives-ouvertes.fr/hal-00482946

P. Brucker, A. Drexl, R. Mohring, K. Neumann, and E. Pesch, Resource-constrained project scheduling: Notation, classification, models, and methods, European Journal of Operational Research, vol.112, issue.1, pp.3-41, 1999.
DOI : 10.1016/S0377-2217(98)00204-5

F. Gasperoni and U. Schwiegelshohn, GENERATING CLOSE TO OPTIMUM LOOP SCHEDULES ON PARALLEL PROCESSORS, Parallel Processing Letters, vol.04, issue.04, pp.391-403, 1994.
DOI : 10.1142/S0129626494000363

J. Wang, C. Eisenbeis, M. Jourdan, and B. Su, Decomposed software pipelining: A new perspective and a new approach, International Journal of Parallel Programming, vol.19, issue.7, pp.351-373, 1994.
DOI : 10.1007/BF02577737

A. Munier, M. Queyranne, and A. S. Schulz, Approximation Bounds for a General Class of Precedence Constrained Parallel Machine Scheduling Problems, pp.367-382, 1998.
DOI : 10.1007/3-540-69346-7_28

H. C. Chou and C. P. Chung, UPPER BOUND ANALYSIS OF SCHEDULING ARBITRARY-DELAY INSTRUCTIONS ON TYPED PIPELINED PROCESSORS, International Journal of High Speed Computing, vol.04, issue.04, pp.301-312, 1992.
DOI : 10.1142/S0129053392000146

C. E. Leiserson and J. B. Saxe, Retiming synchronous circuitry, Algorithmica, vol.9, issue.No. 1, p.797, 1988.
DOI : 10.1007/BF01759032
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.368.3222