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High-throughput LDPC decoder on low-power embedded processors

Abstract : Real-time efficient implementations of LDPC decoders have long been considered exclusively reachable using dedicated hardware architectures. Attempts to implement LDPC decoders on CPU and GPU devices have lead to high power consumptions as well as high processing latencies that are incompatible with most embedded and mobile transmission systems. In this letter, we propose ARM-based decoders that go from 50 to 100 Mbps while executing 10 layered-decoding iterations. We hereby demonstrate that efficient LDPC decoders can be implemented on a low-power programmable architecture. The proposed decoders are competitive with recent GPU related works. Therefore, software LDPC decoders constitute a response to software defined radio constraints.
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Contributor : Bertrand Le Gal <>
Submitted on : Thursday, March 10, 2016 - 2:59:52 PM
Last modification on : Thursday, September 12, 2019 - 8:38:07 AM


  • HAL Id : hal-01286228, version 1


Bertrand Le Gal, Christophe Jego. High-throughput LDPC decoder on low-power embedded processors. IEEE Communications Letters, Institute of Electrical and Electronics Engineers, 2015, 19 (11), pp.1861-1864. ⟨hal-01286228⟩



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