Exploring the Effect of LUT and Arity Size on a Tree-based Application Specific Inflexible FPGA

Umer Farooq (1) , Husain Parvez (1) , Emna Amouri (1) , Habib Mehrez (1) , Zied Marrakchi (1)

1 CIAN - Circuits Intégrés Numériques et Analogiques

An application specific inflexible FPGA (ASIF) is an FPGA with reduced flexibility and improved density. An ASIF is reduced from an FPGA for a predefined set of applications that operate at mutually exclusive times. This work presents a new tree-based ASIF and uses a set of 16 MCNC benchmarks to explore the effect of lookup table (LUT) and arity size on it and results are then compared with those of mesh-based ASIF. For tree-based ASIF, LUT size is varied from 3 to 7 while arity size is varied from 4 to 8 and 16. Experimental results show that smaller LUTs with higher arity sizes produce good area results but poor performance results. Finally experimental results show that LUT 4 with arity 16 gives best area-delay product and compared to mesh-based ASIF, this combination gives 12% routing area gain.

Domaines: Informatique [cs]

Umer Farooq, Husain Parvez, Emna Amouri, Habib Mehrez, Zied Marrakchi. Exploring the Effect of LUT and Arity Size on a Tree-based Application Specific Inflexible FPGA. International conference on Design & Technology of Integrated Systems (DTIS), Apr 2011, Athens, Greece. pp.1-6, ⟨10.1109/DTIS.2011.5941426⟩. ⟨hal-01284605⟩