J. Bajard, L. Imbert, and G. A. Jullien, Parallel Montgomery Multiplication in GF (2^k) Using Trinomial Residue Arithmetic, 17th IEEE Symposium on Computer Arithmetic (ARITH'05), pp.164-171, 2005.
DOI : 10.1109/ARITH.2005.34
URL : https://hal.archives-ouvertes.fr/lirmm-00106024

P. Bulens, F. Standaert, J. Quisquater, P. Pellegrin, and G. Rouvroy, Implementation of the AES-128 on Virtex-5 FPGAs, Progress in Cryptology - AFRICACRYPT, pp.16-26, 2008.
DOI : 10.1007/978-3-540-68164-9_2

H. Fan and M. A. Hasan, A New Approach to Subquadratic Space Complexity Parallel Multipliers for Extended Binary Fields, IEEE Transactions on Computers, vol.56, issue.2, pp.224-233, 2007.
DOI : 10.1109/TC.2007.19

T. Good and M. Benaissa, AES on FPGA from the Fastest to the Smallest, Cryptographic Hardware and Embedded Systems -CHES, pp.427-440, 2005.
DOI : 10.1007/11545262_31

J. A. Gordon, Very simple method to find the minimum polynomial of an arbitrary nonzero element of a finite field, Electronics Letters, vol.12, issue.25, pp.663-664, 1976.
DOI : 10.1049/el:19760508

K. U. Jarvinen, M. T. Tommiska, and J. O. Skyttae, A fully pipelined memoryless 17.8 Gbps AES-128 encryptor, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays , FPGA '03, pp.207-215, 2003.
DOI : 10.1145/611817.611848

S. Lemsitzer, J. Wolkerstorfer, N. Felber, and M. Braendli, Multi-gigabit GCM-AES Architecture Optimized for FPGAs, Cryptographic Hardware and Embedded Systems -CHES, pp.227-238, 2007.
DOI : 10.1007/978-3-540-74735-2_16

E. D. Mastrovito, VLSI Architectures for Computation in Galois Fields, 1991.

D. A. Mcgrew and J. Viega, The Galois/Counter Mode of Operation (GCM), 2005.

C. Paar, A new architecture for a parallel finite field multiplier with low complexity based on composite fields, IEEE Transactions on Computers, vol.45, issue.7, pp.856-861, 1996.
DOI : 10.1109/12.508323

P. Patel, Parallel multiplier designs for the Galois/counter mode of operation, 2008.

A. Satoh, High-speed hardware architectures for authenticated encryption mode GCM, 2006 IEEE International Symposium on Circuits and Systems, pp.4831-4834, 2006.
DOI : 10.1109/ISCAS.2006.1693712

A. Satoh, High-Speed Parallel Hardware Architecture for Galois Counter Mode, 2007 IEEE International Symposium on Circuits and Systems, pp.1863-1866, 2007.
DOI : 10.1109/ISCAS.2007.378278

A. Satoh, T. Sugawara, and T. Aoki, High-Speed Pipelined Hardware Architecture for Galois Counter Mode, 10th International Conference -ISC, pp.1863-1866, 2007.
DOI : 10.1007/978-3-540-75496-1_8

F. X. Standaert, G. Rouvroy, J. Quisquater, and J. Legat, Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs, Cryptographic Hardware and Embedded Systems -CHES, volume 2779 of LNCS, pp.334-350, 2003.
DOI : 10.1007/978-3-540-45238-6_27