AEGIS-Based Efficient Solution for Secure Reconfiguration of FPGAs

Abstract : The reconfiguration of FPGAs includes downloading the bit- stream file which contains the new design on the FPGA. The option to reconfigure FPGAs dynamically opens up the threat of stealing the Intellectual Property (IP) of the de- sign. Since the configuration is usually stored in external memory, this can be easily tapped and read out by an eaves- dropper. This work presents a low cost solution in order to secure the reconfiguration of FPGAs. The proposed solution is based on an efficient-compact hardware implementation for AEGIS which is considered one of the candidates to the competition of CAESAR 1. The proposed architecture de- pends on using 1/4 AES-round for reducing the consumed area. We evaluated the presented design using 90 and 65 nm technologies. Our comparison to existing AES-based schemes reveals that the proposed design is better in terms of the hardware performance (Thr./mm2).
Complete list of metadatas

https://hal.sorbonne-universite.fr/hal-01259069
Contributor : Roselyne Chotin <>
Submitted on : Tuesday, January 19, 2016 - 6:46:55 PM
Last modification on : Thursday, March 21, 2019 - 2:30:34 PM

Identifiers

Citation

Karim Moussa Ali Abdellatif, Roselyne Chotin-Avot, Habib Mehrez. AEGIS-Based Efficient Solution for Secure Reconfiguration of FPGAs. Cryptography and Security in Computing Systems, Jan 2016, Prague, Czech Republic. pp.37-40, ⟨10.1145/2858930.2858937⟩. ⟨hal-01259069⟩

Share

Metrics

Record views

272