From system design to clock skew impact study in parallel sigma delta modulators using frequency band decomposition

Abstract : This paper presents the study of a novel parallel architecture of analog-to-digital converters (ADCs) based on sigma delta modulators using frequency band decomposition (FBD). This architecture is intended for wideband applications with a fractional bandwidth equal to 40 % and composed of four channels of 6 th order band-pass discrete time (DT) sigma delta modulators with single-bit quantization. The simulation results prove that this architecture is able to provide a signal-to-noise ratio (SNR) over 50 dB. These results satisfy the wideband standard requirements. However, parallel architectures are sensitive to channel mismatches. In this paper, we are interested in studying the robustness of our FBD architecture to clock skew mismatch errors. It is shown that the clock skew causes the SNR to decrease by at most 6 dB.
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https://hal.archives-ouvertes.fr/hal-01258564
Contributor : Dominique Dallet <>
Submitted on : Wednesday, January 20, 2016 - 4:59:49 PM
Last modification on : Thursday, October 17, 2019 - 12:36:09 PM

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  • HAL Id : hal-01258564, version 1

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Rihab Lahouli, Manel Ben Romdhane, Chiheb Rebai, Dominique Dallet. From system design to clock skew impact study in parallel sigma delta modulators using frequency band decomposition. 19th Symposium IMEKO TC 4 Symposium and 17th IWADC Workshop Advances in Instrumentation and Sensors Interoperability, Jul 2013, Barcelone, Spain. ⟨hal-01258564⟩

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