Branch Strategies to Optimize Decision Trees for Wide-Issue Architectures
Résumé
Branch predictors are associated with critical design issues for nowadays instruction greedy processors. We study two important domains where the
optimization of decision trees — implemented through switch - case or nested if - then - else constructs — makes the precise modeling of these hardware mechanisms determining for performance: compute-intensive libraries with versioning
and cloning, and high-performance interpreters. Against common belief, the complexity of recent microarchitectures does not necessarily hamper the design of accurate cost models, in the special case of decision trees. We build a simple model
that illustrates the reasons for which decision tree performance is predictable.
Based on this model, we compare the most significant code generation strategies
on the Itanium2 processor. We show that no strategy dominates in all cases, and
although they used to be penalized by traditional superscalar processors, indirect
branches regain a lot of interest in the context of predicated execution and delayed branches. We validate our study with an improvement from 15% to 40%
over Intel ICC compiler for a Daxpy code focused on short vectors.
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