. Kalray, The MPPA hardware architecture, 2012.

E. Fleury and P. Fraigniaud, A general theory for deadlock avoidance in wormhole-routed networks, IEEE Transactions on Parallel and Distributed Systems, vol.9, issue.7, pp.626-638, 1998.
DOI : 10.1109/71.707539
URL : https://hal.archives-ouvertes.fr/inria-00098494

J. Duato, A new theory of deadlock-free adaptive routing in wormhole networks, IEEE Transactions on Parallel and Distributed Systems, vol.4, issue.12, pp.1320-1331, 1993.
DOI : 10.1109/71.250114

B. D. De-dinechin, Y. Durand, D. Van-amstel, and A. Ghiti, Guaranteed Services of the NoC of a Manycore Processor, Proceedings of the 2014 International Workshop on Network on Chip Architectures, NoCArc '14, pp.11-16, 2014.
DOI : 10.1145/2685342.2685344
URL : https://hal.archives-ouvertes.fr/hal-01102657

J. Boudec and P. Thiran, Network Calculus: A Theory of Deterministic Queuing Systems for the Internet, 2001.

A. Garcia, L. Johansson, M. Jonsson, and M. Weckstèn, Guaranteed periodic real-time communication over wormhole switched networks, 13 th Int. Conf. on Parallel and distributed computing systems (ISCA), pp.632-639, 2000.

B. Jacob, S. Ng, and D. Wang, Memory Systems: Cache, DRAM, Disk, 2007.

P. Atanassov and P. Puschner, Impact of DRAM Refresh on the Execution Time of Real-Time Tasks, Proc. IEEE International Workshop on Application of Reliable Computing and Communication, pp.29-34, 2001.

. Micron, 4Gb: x4, x8, x16 DDR3L SDRAM Description, 2011.

O. Mutlu and T. Moscibroda, Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007), pp.146-160, 2007.
DOI : 10.1109/MICRO.2007.21

J. Korst, E. H. Aarts, J. K. Lenstra, and J. Wessels, Periodic Multiprocessor Scheduling, Proceedings on Parallel Architectures and Languages Europe : Volume I: Parallel Architectures and Algorithms, ser. PARLE '91, pp.166-178, 1991.

B. Akesson, K. Goossens, and M. Ringhofer, Predator, Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis , CODES+ISSS '07, pp.251-256, 2007.
DOI : 10.1145/1289816.1289877

M. Paolieri, E. Quiones, F. Cazorla, and M. Valero, An Analyzable Memory Controller for Hard Real-Time CMPs Embedded Systems Letters, pp.86-90, 2009.

J. Reineke, I. Liu, H. D. Patel, S. Kim, and E. A. Lee, PRET DRAM controller, Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, CODES+ISSS '11, pp.99-108, 2011.
DOI : 10.1145/2039370.2039388

Y. Krishnapillai, Z. P. Wu, and R. Pellizzoni, A Rank-Switching, Open-Row DRAM Controller for Time-Predictable Systems, 2014 26th Euromicro Conference on Real-Time Systems, pp.27-38, 2014.
DOI : 10.1109/ECRTS.2014.37

Y. Ding, L. Wu, and W. Zhang, Bounding Worst-Case DRAM Performance on Multicore Processors, Journal of Computing Science and Engineering, vol.7, issue.1, pp.53-66, 2013.
DOI : 10.5626/JCSE.2013.7.1.53

Z. P. Wu, Y. Krish, and R. Pellizzoni, Worst Case Analysis of DRAM Latency in Multi-requestor Systems, 2013 IEEE 34th Real-Time Systems Symposium, pp.372-383, 2013.
DOI : 10.1109/RTSS.2013.44

H. Kim, D. De-niz, B. Andersson, M. Klein, O. Mutlu et al., Bounding memory interference delay in COTS-based multi-core systems, 2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS), 2014.
DOI : 10.1109/RTAS.2014.6925998

H. Yun and R. Pellizzoni, Parallelism-Aware Memory Interference Delay Analysis for COTS Multicore Systems, 2015 27th Euromicro Conference on Real-Time Systems, 2014.
DOI : 10.1109/ECRTS.2015.24

H. Yun, G. Yao, R. Pellizzoni, M. Caccamo, and L. Sha, Mem- Guard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms, 19th Real-Time and Embedded Technology and Applications Symposium (RTAS'13), pp.55-64, 2013.

T. Carle, M. Djemal, D. Potop-butucaru, and R. Simone, Static Mapping of Real-Time Applications onto Massively Parallel Processor Arrays, 2014 14th International Conference on Application of Concurrency to System Design, 2014.
DOI : 10.1109/ACSD.2014.19
URL : https://hal.archives-ouvertes.fr/hal-01095130