Substrate modeling to improve reliability of high voltage technologies

Camillo Stefanucci 1 Pietro Buccella 1 Yasser Moursy 2 Hao Zou 2 Ramy Iskander 2 Maher Kayal 1 Jean-Michel Sallese 1
1 EPFL - Ecole Polytechnique Fédérale de Lausanne
2 CIAN - Circuits Intégrés Numériques et Analogiques
LIP6 - Laboratoire d'Informatique de Paris 6
Abstract : —In Smart Power ICs there is the need of new substrate models to be integrated in the design flow of power circuits. This work reports the latest results regarding the substrate modeling methodology based on three-dimensional lumped components extraction of diodes, resistors and contacts. The substrate network including lateral and vertical parasitic bipolar transistor can be automatically created from any chip layout including temperature and geometry variations. In such a way fast dc and transient analysis can be carried out in early design stages to improve reliability of high voltage ICs. Since the high variability and complexity on modern Smart Power technologies, a flexible model is required. This work discusses all the features related to technology variations. Circuit simulator results are then compared with TCAD simulations.
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UPMC | LIP6 | LIP6-CIAN | SORBONNE-UNIVERSITE | SU-SCIENCES

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Camillo Stefanucci, Pietro Buccella, Yasser Moursy, Hao Zou, Ramy Iskander, et al.. Substrate modeling to improve reliability of high voltage technologies. 20th International Mixed-Signal Testing Workshop (IMSTW), 2015, Paris, Jun 2015, Paris, France. ⟨10.1109/IMS3TW.2015.7177884⟩. ⟨hal-01228157⟩

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