Modeling, Design and Verification Platform using SystemC AMS

Yao Li 1 Ramy Iskander 1 Marie-Minerve Louërat 1
1 CIAN - Circuits Intégrés Numériques et Analogiques
LIP6 - Laboratoire d'Informatique de Paris 6
Abstract : This paper proposes a modeling, design and verification platform with a fast sizing and biasing methodology. We introduce a simple and efficient method to implement an interface between nonconservative system level models and their circuit level realizations. Simulation tools such as SystemC AMS and Spice simulators are combined with a sizing and biasing tool. Moreover, a transient simulation method is proposed to simulate nonlinear dynamic behavior of complete mixed-signal systems. A verification testbench is introduced to monitor the effect of circuit-level nonidealities on system-level performances. The proposed platform is used to design and verify a 3-stage 6-bits Pipeline ADC. The simulation results prove the effectiveness of the proposed methodology.
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Conference papers
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https://hal.archives-ouvertes.fr/hal-01217487
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Submitted on : Monday, October 19, 2015 - 4:29:16 PM
Last modification on : Thursday, March 21, 2019 - 2:33:11 PM

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Yao Li, Ramy Iskander, Marie-Minerve Louërat. Modeling, Design and Verification Platform using SystemC AMS. 15th International Symposium on Quality Electronic Design, ISQED 2014, Mar 2014, Santa Clara, CA, United States. pp.39-46, ⟨10.1109/ISQED.2014.6783304⟩. ⟨hal-01217487⟩

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