Generation of UVM compliant Test Benches for Automotive Systems using IP-XACT with UVM-SystemC and SystemC AMS extensions

Ronan Lucas , Emmanuel Vaumorin , Philippe Cuenot , Yao Li (1) , Zhi Wang (1) , Marie-Minerve Louërat (1) , Jean-Paul Chaput (2) , François Pêcheux (1) , Ramy Iskander (1) , Martin Barnasconi , Thilo Vörtler , Karsten Einwich

1 CIAN - Circuits Intégrés Numériques et Analogiques
2 LIP6 - Laboratoire d'Informatique de Paris 6

This paper will present a methodology and flow to automate the test bench creation for automotive heterogeneous HW/SW systems, using SystemC, SystemC-AMS and IP-XACT. The UVM foundation elements such as test, environment, UVC (Universal Verification Component), transactions and associated configuration objects are introduced, which are packaged by means of IP-XACT vendor extensions. The benefit is to facilitate the (re)use of UVM components and environments by providing a readable and configurable test platform description, to trace the requirements of tests, and to generate automatically the entire UVM environment and simulation build flow after configuration of the test scenario. The automation technology is based on IP-XACT and uses new capabilities of the Magillem tools solution.

Domaines: Informatique [cs]

Ronan Lucas, Emmanuel Vaumorin, Philippe Cuenot, Yao Li, Zhi Wang, et al.. Generation of UVM compliant Test Benches for Automotive Systems using IP-XACT with UVM-SystemC and SystemC AMS extensions. Design and Verification Conference and Exhibition (DVCON Europe), Oct 2014, Munich, Germany. ⟨hal-01217214⟩