Split ADC digital background calibration for high speed SHA-less pipeline ADCs

Abstract : A bottom plate sampling switch sharing technique is proposed to enable split ADC calibration with high frequency inputs for Sample and Hold Amplifier-less (SHA-less) pipeline ADCs. The shared bottom plate switch ensures that both halves of the ADC sample the input at the same time, which restores the calibration accuracy for fast varying inputs without the presence of a front-end SHA, thereby significantly reducing area and power consumption. For further power reduction, a feedforward two stage amplifier has been used to push the speed of the amplifier at lower current consumption and low supply voltage. A 12-bit 200 MS/s pipeline ADC has been designed in 40 nm CMOS technology, and the transistor level simulations of the ADC prove the efficiency of the proposed technique to restore the split ADC calibration accuracy in SHA-less pipeline ADCs.
Document type :
Conference papers
Complete list of metadatas

https://hal.archives-ouvertes.fr/hal-01216634
Contributor : Lip6 Publications <>
Submitted on : Friday, October 16, 2015 - 3:28:55 PM
Last modification on : Thursday, March 21, 2019 - 2:31:15 PM

Identifiers

Citation

Hussein Adel, Marc Sabut, Roger Petigny, Marie-Minerve Louërat. Split ADC digital background calibration for high speed SHA-less pipeline ADCs. International Symposium on Circuits and Systems (ISCAS), Jun 2014, Melbourne, Australia. pp.1143-1146, ⟨10.1109/ISCAS.2014.6865342⟩. ⟨hal-01216634⟩

Share

Metrics

Record views

107