Dynamic Data Flow Analysis for NoC Based Application Synthesis
Résumé
Network-on-Chip (NoC) is an interesting communication
fabric for multi processing element architectures that
benefits from the parallelism of algorithms. We present a method
that uses a symbolic execution technique to extract the parallelism
of an application to be mapped on FPGAs using the flexibility of
a NoC communication infrastructure and the properties of a high
level programming language. An application specific hardware is
then generated using a High Level Synthesis flow. We provide a
dedicated mechanism for data paths reconfiguration that allows
different applications to run on the same set of processing
elements. Thus, the output design is programmable and has a
processor-less distributed control. This approach of using NoCs
enables us to automatically design generic architectures that can
be used on FPGA servers for High Performance Reconfigurable
Computing.We validate our method on binomial tree applications
used for option pricing on FPGAs.