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Parallel Image Gradient Extraction Core For FPGA-based Smart Cameras

Abstract : One of the biggest efforts in designing pervasive Smart Camera Networks (SCNs) is the implementation of complex and computationally intensive computer vision algorithms on resource constrained embedded devices. For low-level processing FPGA devices are excellent candidates because they support massive and fine grain data parallelism with high data throughput. However, if FPGAs offers a way to meet the stringent constraints of real-time execution, their exploitation often require significant algorithmic reformulations. In this paper, we propose a reformulation of a kernel-based gradient computation module specially suited to FPGA implementations. This resulting algorithm operates on-the-fly, without the need of video buffers and delivers a constant throughput. It has been tested and used as the first stage of an application performing extraction of Histograms of Oriented Gradients (HOG). Evaluation shows that its performance and low memory requirement perfectly matches low cost and memory constrained embedded devices.
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Submitted on : Monday, September 28, 2015 - 9:34:36 AM
Last modification on : Tuesday, April 20, 2021 - 11:22:14 AM
Long-term archiving on: : Tuesday, December 29, 2015 - 10:18:11 AM


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  • HAL Id : hal-01199197, version 2


Luca Maggiani, Cédric Bourrasset, François Berry, Jocelyn Sérot, Matteo Petracca, et al.. Parallel Image Gradient Extraction Core For FPGA-based Smart Cameras. International Conference on Distributed Smart Cameras, ACM, Sep 2015, Seville, Spain. ⟨hal-01199197v2⟩



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