UVM-SystemC-AMS Framework for System-Level Verification and Validation of Automotive Use Cases

Abstract : Current trend is to increase the overall use of electronic systems in daily life. Exemplarily, the complexity of automotive Electronic Control Unit (ECU) systems is rising due to the number of components involved and the tighter interactions between these heterogeneous components (analog, digital hardware or software), resulting in a more and more challenging verification. In this paper, we show that the Universal Verification Methodology (UVM), initially developed for digital systems, can successfully be extended to analog and mixed signal systems. We introduce the UVM-SystemC-AMS framework for functional verification based on SystemC and its AMS extension SystemC AMS. Using two automotive case studies we demonstrate the flexibility of our approach both for simulation based verification and lab based validation using a Hardware In the Loop (HIL) system.
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Journal articles
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https://hal.archives-ouvertes.fr/hal-01197195
Contributor : Lip6 Publications <>
Submitted on : Friday, September 11, 2015 - 11:58:43 AM
Last modification on : Thursday, March 21, 2019 - 2:40:22 PM

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Martin Barnasconi, Manfred Dietrich, Karsten Einwich, Thilo Vörtler, Jean-Paul Chaput, et al.. UVM-SystemC-AMS Framework for System-Level Verification and Validation of Automotive Use Cases. IEEE Design & Test, IEEE, 2015, pp.76-86. ⟨10.1109/MDAT.2015.2427260⟩. ⟨hal-01197195⟩

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