Thermal management of lateral GaN power devices

Chenjiang Yu (1) , Éric Labouré (1) , Cyril Buttay (2)

1 GeePs - Laboratoire Génie électrique et électronique de Paris
2 EE - Ampère, Département Energie Electrique

This article investigates several thermal management techniques for GaN transistors with a Wafer-Level Packaging (WLP): advanced techniques are used to mount them on Direct-Bonded Copper (DBC) ceramic substrates, with the heat removed either through the topside of the die (as recommended by the manufacturer), or through the backside. The thermal resistance of the assembly is measured in the different configurations, for different die thicknesses. The paper describes the manufacturing process and the thermal simulation and experimental results will be shown.

Mots clés: flip-chip; 3D packaging; thermal management; Flex circuit; GaN power device

Domaines: Sciences de l'ingénieur [physics]

Chenjiang Yu, Éric Labouré, Cyril Buttay. Thermal management of lateral GaN power devices. 2015 IEEE IWIPP, May 2015, Chicago, IL, United States. ⟨10.1109/IWIPP.2015.7295973⟩. ⟨hal-01196527⟩