Hardware implementation of discrete stochastic arithmetic

Roselyne Chotin-Avot 1 Habib Mehrez 1
1 CIAN - Circuits Intégrés Numériques et Analogiques
LIP6 - Laboratoire d'Informatique de Paris 6
Abstract : In this paper we present a hardware implementation of the Discrete Stochastic Arithmetic (DSA) which is based on CESTAC (Controle et Estimation STochastique des Arrondis de Calculs), a method of controlling round-off errors in floating-point scientific computations. Real-time software implementation of this method suffers from computation bottlenecks. This paper gives a hardware alternative that would significantly accelerate the computation. The proposed architecture is based on a Stochastic Floating-Point Unit (SFPU) which performs discrete stochastic operations. This SFPU has been integrated in a coprocessor, used in a complete System on Chip (SoC).
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https://hal.archives-ouvertes.fr/hal-01195967
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Submitted on : Tuesday, September 8, 2015 - 5:49:13 PM
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Roselyne Chotin-Avot, Habib Mehrez. Hardware implementation of discrete stochastic arithmetic. Numerical Algorithms, Springer Verlag, 2004, 37 (1-4), pp.21-33. ⟨10.1023/B:NUMA.0000049455.07441.ee⟩. ⟨hal-01195967⟩

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