Timed Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata

Abstract : Using a variant of Clariso-Cortadella’s parametric method for verifying asynchronous circuits, we analyse some crucial timing behaviors of the architecture of SPSMALL memory, a commercial product of STMicroelectronics. Using the model of parametric timed automata and model checker HYTECH, we formally derive a set of linear constraints that ensure the correctness of the response times of the memory. We are also able to infer the constraints characterizing the optimal setup timings of input signals. We have checked, for two different implementations of this architecture, that the values given by our model match remarkably with the values obtained by the designer through electrical simulation.
Document type :
Journal articles
Complete list of metadatas

https://hal.archives-ouvertes.fr/hal-01195912
Contributor : Lip6 Publications <>
Submitted on : Tuesday, September 8, 2015 - 4:27:50 PM
Last modification on : Friday, May 24, 2019 - 5:31:27 PM

Links full text

Identifiers

Citation

Rémy Chevallier, Emmanuelle Encrenaz, Laurent Fribourg, Weiwen Xu. Timed Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata. Formal Methods in System Design, Springer Verlag, 2009, 34 (1), pp.59-81. ⟨10.1007/s10703-008-0061-x⟩. ⟨hal-01195912⟩

Share

Metrics

Record views

118