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Assignment of Vertical Links to Routers in Vertically-Partially-Connected 3D-NoCs

Abstract : This paper addresses elevator assignment in vertically-partially-connected 3-D-networks-on-chip (NoCs). Elevators are vertical links between dies. Because of yield issues, Through-Silicon-Via (TSV) cost, and heterogeneity in dimension, topology, and technology of different dies, vertically-partially-connected topologies seem unavoidable in the emerging 3-D-NoCs as opposed to fully-connected topologies. In such partially-connected topologies, as there are fewer elevators than routers, the assignment of elevators to routers becomes a new 3-D-specific optimization problem. An improper assignment can lead to dramatic network performance degradation. This paper proposes an elevator assignment method for best-effort wormhole 3-D-NoCs to improve the average network performance. Experimental results show an improvement of about 90% even compared to a greedy (intrinsically good) initial assignment.
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https://hal.archives-ouvertes.fr/hal-01195897
Contributor : Lip6 Publications <>
Submitted on : Tuesday, September 8, 2015 - 4:13:09 PM
Last modification on : Friday, January 8, 2021 - 5:32:08 PM

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Sahar Foroutan, Abbas Sheibanyrad, Frédéric Pétrot. Assignment of Vertical Links to Routers in Vertically-Partially-Connected 3D-NoCs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2014, 33 (8), pp.1208-1218. ⟨10.1109/TCAD.2014.2323219⟩. ⟨hal-01195897⟩

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