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Communication Dans Un Congrès Année : 2015

An Energy-Aware Scheduler for Dynamically Reconfigurable Multi-Core Systems

Résumé

This paper describes an energy-aware scheduling approach intended for use in heterogeneous multiprocessors supporting hardware acceleration with Dynamic and Partial Re-configuration. Scheduler decisions rely on pragmatic power and energy models to map the load across cores and reconfigurable regions with regards to the actual power costs. Results on a multithreaded H.264/AVC profile decoder with three possible hardware functions on a Xilinx Zynq based platform report energy gains up to 44.1% over full software execution and 49.6% over static hardware / software execution, while ensuring real-time decoding requirement.
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Dates et versions

hal-01192796 , version 1 (14-03-2016)

Identifiants

Citer

Robin Bonamy, Sébastien Bilavarn, Fabrice Muller. An Energy-Aware Scheduler for Dynamically Reconfigurable Multi-Core Systems. 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2015, Jun 2015, Bremen, Germany. pp.1-6, ⟨10.1109/ReCoSoC.2015.7238084⟩. ⟨hal-01192796⟩
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