Methodological Framework for NoC Resources Dimensioning on FPGAs

Virginie Fresse (1) , Catherine Combes (1) , Matthieu Payet (1) , Frédéric Rousseau (2)

1 LHC - Laboratoire Hubert Curien
2 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

The two main challenges involved in prototyping a SoC (System-On-Chip) on a FPGA (field programmable gate array) are optimal tuning of the communication architecture according to the task graph of an application, and dimensioning the FPGA resources. In this paper, we present a methodological framework to estimate the number of resources required for a given communication architecture and task graph. Data analysis was based on a set of synthesized results for a given on-chip network. The most appropriate models were identified using a data mining approach. The evaluation of the models shows that the relative error is less than 5% in most cases. It is therefore possible to estimate the required resources in a short exploration time, without the synthesis steps.

Mots clés: NoC on FPGA; Mathematical models; resource dimensionning; methodological framework; area estimation

Domaines: Systèmes embarqués; Mathématiques [math]

Virginie Fresse, Catherine Combes, Matthieu Payet, Frédéric Rousseau. Methodological Framework for NoC Resources Dimensioning on FPGAs. 2nd International Workshop on Design and Performance of Networks on Chip, Aug 2015, Belfort, France. ⟨hal-01186066⟩