FPGA implementation of a shuffled iterative bit-interleaved coded modulation receiver

Abstract : Signal Space Diversity (SSD) has been lately adopted into the second generation of the terrestrial digital video broadcasting standard DVB-T2. In this paper, a bit-interleaved coded modulation receiver for the DVB-T2 standard is detailed. An LDPC decoder based on a vertical layered schedule is the main novelty of this work. It enables an efficient exchange of extrinsic information between the rotated demapper and the LDPC decoder if an iterative receiver is considered. The FPGA prototyping of the resultant architecture is then described. Low architecture complexity and good performance represent the main features of the proposed receiver.
Complete list of metadatas

https://hal.archives-ouvertes.fr/hal-01183873
Contributor : Bibliothèque Télécom Bretagne <>
Submitted on : Tuesday, August 11, 2015 - 6:48:02 PM
Last modification on : Thursday, October 17, 2019 - 12:36:43 PM

Identifiers

  • HAL Id : hal-01183873, version 1

Citation

Meng Li, Charbel Abdel Nour, Christophe Jego, Jianxiao Yang, Catherine Douillard. FPGA implementation of a shuffled iterative bit-interleaved coded modulation receiver. SOC-SIP : journée du groupe de recherche System On Chip - System In Package, Jun 2011, Lyon, France. ⟨hal-01183873⟩

Share

Metrics

Record views

215