Feasibility Analysis for Robustness Quantification by Symbolic Model Checking

Abstract : We propose and investigate a robustness evaluation procedure for sequential circuits subject to particle strikes inducing bit-flips in memory elements. We define a general fault model, a parametric reparation model and quantitative measures reflecting the robustness capability of the circuit with respect to these fault and reparation models. We provide algorithms to compute these metrics and show how they can be interpreted in order to better understand the robustness capability of several circuits (a simple circuit coming from the VIS distribution, circuits from the itc-99 benchmarks and a CAN-Bus interface).
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Article dans une revue
Formal Methods in System Design, Springer Verlag, 2011, 39 (2), pp.165-184. <10.1007/s10703-011-0121-5>
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https://hal.archives-ouvertes.fr/hal-01176355
Contributeur : Lip6 Publications <>
Soumis le : mercredi 15 juillet 2015 - 12:00:09
Dernière modification le : jeudi 16 juillet 2015 - 01:03:36

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Souheib Baarir, Cécile Braunstein, Emmanuelle Encrenaz, Jean-Michel Ilié, Isabelle Mounier, et al.. Feasibility Analysis for Robustness Quantification by Symbolic Model Checking. Formal Methods in System Design, Springer Verlag, 2011, 39 (2), pp.165-184. <10.1007/s10703-011-0121-5>. <hal-01176355>

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