Sparse channelizer for FPGA-based simultaneous multichannel DRM30 receiver

Brunel Happi Tietche (1) , Olivier Romain (2) , Bruce Denby (3)

1 ETIS - UMR 8051 - Equipes Traitement de l'Information et Systèmes
2 ASTRE [Cergy-Pontoise]
3 ESPCI Paris - Ecole Superieure de Physique et de Chimie Industrielles de la Ville de Paris

The paper describes a channelization architecture that simultaneously extracts all radio stations in the DRM30 standard, that is intended to be an important part of a future receiver to simultaneously demodulate the entire 0 - 30 MHz broadcast band for content and metadata indexing applications. The system, which contains overlap-add and Goertzel algorithms, is implemented on a single Field- Programmable Gate Array (FPGA), thus offering the possibility of use in real time applications. This novel architecture achieves superior efficiency by minimizing multiplication calculational resources, as compared to existing FPGA-based channelizers. Chip resource utilization details and experimental results from the developed prototype are also presented.

Mots clés: Channelization; FPGA; DRM30; Indexing applications

Domaines: Electronique

Brunel Happi Tietche, Olivier Romain, Bruce Denby. Sparse channelizer for FPGA-based simultaneous multichannel DRM30 receiver. IEEE Transactions on Consumer Electronics, 2015, 61 (2), pp.151 - 159. ⟨10.1109/TCE.2015.7150568⟩. ⟨hal-01176123⟩